A single chip solution for integrated powertrain domain control and energy management

Top notch FPCU technology
  • AxEC: Hard real-time control on multiple parallel applications with flexible hardware
  • SiLant: Safe multi-core & processing clusters with guaranteed worst case execution time
  • FHSM: Cybersecure with flexible hardware security module to support current and future threats
  • ISO 26262 ASIL-D & ISO/SAE 21434 compliant

All-in-one capabilities for EV power and energy control

The OLEA U310 is a new addition to Silicon Mobility FPCU portfolio and has been engineered to match the need for powertrain domain control in electrical/electronic architectures with distributed software. The OLEA U310 is built with a unique hybrid and heterogenous architecture embedding multiple software and hardware programmable processing and control units seamlessly integrating functional safety and cybersecurity into its core design, surpassing the capabilities of traditional microcontrollers. It hosts and bridges in one chip the time-based and multi-task software application needs with the critical event-based multi-functions control requirements.

Key Features

  • 2nd generation of FPCU
  • 3x Cortex-R52 @ 350MHz – 2196 DMIPS
  • AxEC 2.0: 2x FLUs @ 175Mhz – 400 GOPS + 9.1 GMAC
  • SILant 2.0: Safe and Determinist Multi-Core/FLU
  • Flexible HSM: HW & SW EVITA Full
  • 8MB of P-Flash, 256kB of D-Flash, 1MB of SRAM
  • CAN FD, CAN XL, Ethernet
  • ISO/SAE 21434 certifieISO 26262 ASIL-D & ISO/SAE 21434 compliant
  • AEC-Q100 Grade 1
  • 292 BGA
OLEA U310 architecture

Key Benefits

High Performance

Discover more


Blog coming soon


Blog coming Soon


Blog coming Soon

With unprecedented performances*

Massive Parallel Data Processing

Max Clock Speed: 350 MHz
CPU Processing Speed: 2194 DMIPS
AxEC Math Acc.Speed: 400 GOPS
AxEC SPU Processing Speed: 9.1 GMAC
AES_CMAC Decryption: 91 MB/s

Fast & Precise Parallel Real-Time Control

PWM Min Resolution: 180 ps
PWM Max Freq.switching: 175 MHz
Inverter Control:
Max Freq. FoC Loop: 1 Mhz
Nb of parallel FoC at Max Freq: 4x
Power Factor Corrector:
Max Freq. Loop: 1 us / 1Mhz
Max Freq. Loop: 1 us/Mhz
Max Phases at Max Freq: 8x

Optimized System Efficiency and Integration

Ex: Optimized Pulse Pattern:
Efficient Improvement: +5%
Motor Downsizing: -25%
Cooling Need Reduction: -35%
DC-link Capacitor downs.: 30x less

Digital Control Integration:
1x OLEA U310 FPCU=
4x Real-time 32b MCU +1xFPGA

*Performance varies by use, configuration and other factors. For more information contact us.

Design your E-powertrain function grouping

The OLEA U310 chip simplifies complex system design by replacing up to 6 microcontrollers and efficiently controlling multiple functions in parallel, including inverters, motors, gearboxes, DC-DC, OBC, Auxiliary Functions and more.

Design for the latest automotive control needs

The OLEA U310’s capabilities extend beyond powertrain. This versatile system-on-chip can also be used for:

  • Chassis Control Systems
  • Data Fusion
  • Air compressor
  • Thermal Management System
  • Other Control Systems

By leveraging the OLEA U310’s versatility, EV manufacturers can achieve a more integrated and efficient control system, leading to improved control & performance.

Power by the AxEC

The Advanced eXecution & Event Control (AxEC) unit combines programmable hardware, mathematical coprocessors, and configurable peripherals for direct sensor and actuator interfacing. The programmable hardware is called the Flexible Logic Units (FLU) and lies at the heart of the FPCU architecture. It is a programmable logic fabric equipped with lookup tables, flip-flops, SRAM, and signal processing units, programmed using standard hardware description languages like Verilog or VHDL. The OLEA U® Series introduces the concept of multiple FLU partitions, ranging 1-4.

AxEC handles fast-response-time processing and real-time control, while CPUs manage high-level and low-response-time software. Designers can choose CPU or AxEC for specific tasks, but AxEC typically handles complex processing, reducing CPU usage. Hardware processing ensures rapid, precise responses, regardless of event volume or frequency.

Learn more about the AxEC (blog coming soon)

Safe with OLEA SiLant

The FPCU is designed to meet ASIL-D design ready, the highest level of the automotive safety integrity level of the ISO 26262 functional safety standard. The Safety Integrity Agent (SiLant®) of the OLEA® U Series serves as the central hub for all the safety mechanisms integrated into the FPCU and is responsible for detecting, containing, and reacting to faults in nanoseconds. SiLant® not only monitors latent and transient faults at the semiconductor level but also at the software and system levels.

With the introduction of multi-CPU and multi-FLU, OLEA® U FLU enables safe multitasking and function grouping with unified firmware virtualization from CPU down to FLU level. OLEA U has a deterministic architecture and guarantees Worst-Case Execution Time to design safety-critical applications

Learn more about SiLant (blog coming soon)

Secured with OLEA FHSM

The new generation of FPCU offers the highest protection against actual and future threats. The Flexible Hardware Security Module (FHSM) is a sub-system embedded in OLEA® U Series compliant with EVITA Full and the ISO 21434 automotive cybersecurity standard. It has dedicated programmable hardware that can host custom hardware-accelerated security functions to enhance protection or monitor potential security breaches of the system. This unique feature enables secured software execution and updates and protected real-time communications using an extended span of cryptographic algorithms.

Learn more about the FHSM (blog coming soon)

Contact us for more information

Available Today

Main Features

FunctionsKey Features
AxEC Peripheral
- 48-ch/24-ch: PWMT /inc. HRPWM
- 8-ch: Complex Waveform Generator
- 1x: TEPE (Thermal Engine Position Estimator)
- 10x: SENT
- 3x: PSI-5
- 64-ch: I/O Digital Filter
- 18-ch: ANALOG COMPARE (2 compare/channel)
- 64-ch*: 12-bit SAR ADC @ 4MS/sec
- 2-ch: 16-bit SD ADC @ 330kS/sec
- 2-ch: 12-bit DAC / Soft-Switching support
- 2x 16-ch: Integrated DMA in lockstep
- 4 x 8KB / 64-bit: DPRAM Size/Data width
- 2 x 16-ch: Direct Read Channel to Peripheral (DRC2PRP)
- 2 x 2ch: Direct Read Channel to FLU
- 2 x 64-bit + Buffered: HS Master Interface (MIF)
- 2 x 32-bit + Buffered: Slave interface (SIF)
- 1 x 64-bit: Programing I/F (PIF)
- 10k: Logic Elements (LE)
- 2x: 5K LE FLU partition
- 52x: SPU
- 16-bit/32-bit: SPU data width
- 230 Kbit: integrated RAM
- 150 MHz: Clock Frequency
- 4: Clock Rate domains
- 150 KB: Bitstream size
AxEC Math Accelerator
- 2x: DIV, SQRT, 6x6 MULT
- 2x: Interpolator
- 4x: FIR 8-order
- 4x: IIR 4-order
- 2x: De-modulator
- 3x: EFC - Multi-Core Determinist
- 4x: ESC
+ FLU Programming Protection
+ FLU Incremental Design
+ Virtualization support
+ PWM and DMA in LS
+ ECC end 2 end
+ Configuration registers
+ I/O, clock, resets, supply
-350 MHz Cortex-R52
- 2/1LS + 1LS CPU organization
- 2195: DMIPS
- 8 MB: NVM
- 1 MB: SRAM (+TCM & Cache)
-256KB: Data flash (with FPU prog.)
- 350MHz: 32-bit CPU
- 8 MB: NVM
- 1 MB: SRAM (+TCM & Cache)
-256KB: Data flash (with FPU prog.)
Communication Ports
- 4x/1x: CAN-FD/XL
- 1x: 10M/100M/1Gbit/s Ethernet
- 3x: Master/Slave SPI
- 1x: Master/Slave Octal-SPI
- 4x: UART-LIN 2.3
- 2x: I2C
- 3x: MSC (2 MSC-plus + 1 MSC)
Debug Calibration
- 1x / 1x: JTAG / SWD
+ High-speed TRACE
+ 16-ch AxEC Signal Trace
+ Calibration
- 2x 16-ch: DMA in Lockstep
- 3x: WatchDog
- 2x: CRC
I/Os Supply/Package/Power
- 3.3V: I/O
- 1.8V/ 3.3V: I/O
- 136: PIO
+48/+4: ANIN/ANOUT
+20: ANIN/DIN multiplexing
- 3.3V/1.0V CORE: Supply
- BGA 292: Packages
- 40°C to +125°: Temperature (Ambient)
- 850mA: Consumption @ 350Mhz, Tj=150°C