The Timing generation is meant to compute the delay to apply, within a data rate model, to each block requiring an external resource.

The resources can be DPRAM access, using the ram_controller or peripheral access, using the Sequencer.

This delay is counted in Flu clock cycles and is relative to the start of the algorithm, triggered by the StartPulse signal.

Those delays have no impact on the simulation as they use pipelines (clock rate delays, invisible during data rate simulation).

Category: OLEA® T222 - Target Framework

Press contact

For more information on Silicon Mobility and the OLEA product suite

Contact us

Related Posts

Event May 24, 2024

Join us at PCIM Europe 2024

Join us at PCIM Europe 2024 and visit booth 210, hall 5; we have exciting news to share! For the...

Blog May 17, 2024

Watch now: A single-chip control solution for X-in-1 EV powertrain

A Single-Chip Control Solution For X-in-1 EV Powertrain To Maximizing Performance And Integration The OLEA U FPCU empowers powertrain system...

Event May 14, 2024

Live speech at Autotech Guangzhou on May 15th at 13h00

Silicon Mobility will present “Single-chip control solution for X-in-1 EV powertrains” at Autotech Guangzhou. We are excited to announce a...