To understand, improve or debug a FLU model on Hardware, the user requires access to the internal signals at every FLU-iteration (i.e. at the Data rate). Any signal within the main FLU model can be requested to be logged.
In order to trace a signal (wire), the following conditions should be respected:
– The signal must be directly connected to the output port of a standard subsystem (not a library block).
– The user shall activate the signal logging: right click on a wire, select “Properties”, tab “Logging and accessibility” and then tick “Log signal data”.

The framework will list logged signals and create a structure containing them.
At every main FLU model iteration, the signal values will be copied at their relevant addresses within the DPRAM.