Location: Sophia-Antipolis, France

Job type: Internship

Experience: Student

SILICON MOBILITY SAS (registration number 815 085 659 000 RCS Grasse)

Head office : Les Aqueducs – Bât 2 – 535, route des Lucioles – 06560 Valbonne Sophia-Antipolis

The Automotive industry is living a revolution. Electrification, autonomous driving, diverse mobility, and connectivity are trends that are changing the industry’s rules. Among all decisive topics revolutionizing cars in the next future, Silicon Mobility is committed to supporting the rapid advent of electric and hybrid cars.

Silicon Mobility is a technology leader for cleaner, safer, and smarter mobility. The company designs, develops and sells flexible, real-time, safe, and open semiconductor solutions for the automotive industry used to increase energy efficiency and reduce pollutant emissions while keeping passengers safe.

We are looking for a motivated candidate to join our company in Sophia-Antipolis on the French Riviera.

Please contact us: internship2022@silicon-mobility.com ref. SM-STC002


Role & Missions

Silicon Mobility is developing a System on Chip named OLEA® FPCU. Each FPCU includes several modules (IP). To guarantee the IP does not contain bug, it is necessary to make intensive verification. To do this verification Silicon put in place a method based on SystemVerilog language and Universal Verification Methodology (UVM). The objective of the internship is to put in place this verification method on a new IP module. The intern will be part of the FPCU Front-End team.

This project will be divided in 3 main phases:

  1. Exploration/Definition, the intern will have to acquire knowledge of:
    1. IP Module to verify
    2. SystemVerilog language and Verification method
    3. Write the verification test plan of the IP module
  2. Development, the intern will:
    1. Define and write the structure of the verification
    2. Write the different test scenarios
    3. Set up mechanisms to measure coverage
  3. Verification debug, in this phase the intern will:
    1. Run simulation under QuestaSim environment
    2. Debug the verification tests
    3. Check the requirements tracability

Required Skills and Experience



  • Last year of Masters degree in Electronics Engineering / Microelectronics (BAC+5 or equivalent)


For this internship, we are looking for a candidate with:

  • knowledge of Hardware design for System On Chip (Verilog or VHDL language)
  • Knowledge of an Object Oriented Language (Java or C++)
  • knowledge of SystemVerilog and UVM methodology (would be appreciated)
  • good English level
  • autonomy, rigor, strong team spirit, strong problem-solving skills
  • IP verification methodology
  • UVM methodology
  • SystemVerilog language
  • General knowledge in System On Chip development